A Double Self-Aligned Silicon Bipolar Transistor Utilizing Selectively-Grown Single Crystal Extrinsic Contacts

Feasibility is demonstrated for a unique high speed double self-aligned bipolar junction transistor utilizing monocrystalline silicon base contacts. The transistor is designed for use in high-speed analog or digital applications -where reduced parasitic capacitances and resistances are essential. The device design is unique in reducing extrinsic base/collector capacitance over single self-aligned bipolar transistors by using two relatively independent process techniques. First, bas,e/collector capacitance is reduced by eliminating all misalignment tolerances between the outer edge of the collector and the base contact. Second, by using monocrystalline silicon instead of polycrystalline silicon base contacl,~, the contact area or "footprint u may be reduced without increasing contact resist:snce. Scaled-up versions of the high-speed transistor design were fabricated, electrical.ly tested, and compared with computer simulations. Monocry~jtalline silicon ext:rinsic base contacts were fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) in a reduced pressure chemical vapor deposition reactor using dichlorosilane and HCl in an Hz carrier gas. Single self-aligned trrussistors (SSTs) with polycrystalline silicon contacted emitters wlere fabricated using monocrystalline silicon SEG base extrinsic contacts to examine the emitter/base junction. SSTs demonstrated maximum current gains of approximately 100, with nearly ideal junction behavior. Double self-align'ed transistors (DSiTs) were fabricated using both EL0 and polycrystalline silicon extrinsic base contacts to examine the full device. DSTs yielded maximum current gains of between 100 and 160 with nearly ideal emitter/base junction behavior. Base/collector junctions, however, showed degraded ideality and increased leakage currents over the SSTs. The problem is believed to be related to the increased fabrication complexity required for the DSTs over the SSTs. Reverse biased junction capacitances for SSTs and DSTs were correlated to unit area values and demonstrated good agreement over different device sizes.